(1) Field of the Invention
The present invention relates to a buffer amplifier circuit which has a high operating speed and which is used, for example, as an address buffer circuit in a semiconductor memory device.
(2) Description of the Prior Art
FIG. 1 illustrates a conventional buffer amplifier circuit which is used, for example, as an input buffer circuit such as an address buffer circuit of a semiconductor memory device. The buffer amplifier circuit of FIG. 1 has an inverter structure and comprises a series of connection of an N-channel enhancement type MIS driver transistor Q1 and an N-channel depletion type MIS load transistor Q2. In FIG. 1, A designates an input signal, B designates an output signal and Vcc designates a power supply voltage.
In the buffer amplifier circuit of FIG. 1, when the potential of the input signal A becomes high, the N-channel MIS transistor Q1 is turned on and the output signal B becomes low. On the contrary, when the potential of the input signal A becomes low, the transistor Q1 is turned off and the output signal B becomes high. However, such an operation is guaranteed only when the input signal A has an amply high potential level and an amply low potential level and is in the steady state condition.
As illustrated in FIG. 2A, an internal logic signal A' of a MIS integrated circuit generally has a high potential level (H) of 5V and a low potential level (L) of 0V and, therefore, has an amply large amplitude for driving the inverter circuit of FIG. 1. However, since the input signal to the MIS integrated circuit is transferred through printed circuit patterns and/or lead wires from another TTL circuit, the input signal is attenuated and the amplitude thereof becomes smaller. Moreover, as shown by Aa in FIG. 2A, the actual input signal has oscillations. Therefore, the effective high potential level of the input signal becomes, for example, 2V and the effective low potential level of the input signal becomes, for example, 0.8V. When such an input signal is applied to the inverter circuit of FIG. 1, the operating speed of the inverter circuit becomes slow. This is, the switching time of the output signal B between a high and a low potential level becomes long, and, in the worst case, the switching operation between the high and low potential levels is not effected correctly. The operating speed of the inverter circuit of FIG. 1 is also influenced by the gm characteristics of the transistors Q1 and Q2. For example, when the gms of the transistors Q1 and Q2 are equal to each other, the rise time from the low potential level L to the high potential level H and the fall time from the high potential level to the low potential level of the output signal B are nearly equal to each other as illustrated in FIG. 2B. However the operating speed of such an inverter circuit cannot be fast. If the gm ratio of the transistors Q1 and Q2, i.e., the ratio of the gm of the transistor Q1 to the gm of the transistor Q2 becomes smaller than 1, the rise time of the output signal B becomes short and the fall time of the output signal B becomes long as illustrated by solid lines C1 of FIG. 2A. On the contrary, if the gm ratio is larger than 1, the rise time becomes long and the fall time becomes short as illustrated by dotted lines C2 of FIG. 2A. The gm ratio also influences the threshold potential level Vth, of the input signal A of the inverter circuit of FIG. 1. As illustrated in FIG. 2C, in order to gain the high threshold potential level V"th, it is necessary to make the gm ratio smaller; and, in order to gain the low threshold potential level V'th, it is necessary to make the gm ratio larger. Since it is necessary to adjust the threshold potential Vth to an appropriate level according to the potential levels of the input signal and according to the structure of the pre-stage circuit (e.g. TTL or MIS circuit) connected to the inverter circuit of FIG. 1, the gm ratio and, therefore, the operation speed of the conventional buffer amplifier are limited by the potential levels of the input signal.
If the amplitude of the input signal is amply large, the driver transistor Q1 is overdriven by the input signal and the operation speed of the inverter circuit of FIG. 1 can be fast. However, if the amplitude of the input signal is small, for example if L=0.8V, H=2.0V and Vth=1.4V, the conventional buffer amplifier of FIG. 1 cannot operate fast and reliably.
FIG. 3 illustrates a conventional address buffer circuit of a semiconductor memory device which uses the buffer amplifier circuits of FIG. 1. The address buffer circuits of FIG. 3 comprises the first, the second and the third inverter circuits INV1, INV2 and INV3 which consist of MIS transistor pairs Q3, Q4; Q5, Q6 and Q7, Q8, respectively, and each of which has the same circuit structure as that of the inverter circuit of FIG. 1. The address buffer circuit of FIG. 3 further comprises two output buffer amplifiers BA1 and BA2 which consist of MIS transistor pairs Q9, Q10 and Q11, Q12, respectively and which output buffered address signals A.sub.0 and A.sub.0, respectively.
In the above-mentioned conventional address buffer circuit of FIG. 3, it is necessary to use two stage inverters INV1 and INV2 in order to obtain the address signals having short rise and fall times. This is because, the amplitude of the input address signal A.sub.0 applied to the first inverter INV1 is not always amply large, and therefore, the rise and fall times of the output signal from the first inverter INV1 cannot be short. Therefore, the signal delay of the address buffer amplifier of FIG. 3 is large.